\documentclass{article}
\usepackage{amssymb, amsmath, geometry, multicol}
\usepackage[table, svgnames, dvipsnames]{xcolor}
\usepackage{makecell, cellspace, caption}
\usepackage[europeanresistors]{circuitikz}

\usetikzlibrary{arrows}
\usetikzlibrary{circuits.logic.IEC}

\tikzset{sr/.style={flipflop, flipflop def={
        t1=S, t3=R, t4={\ctikztextnot{Q}},
        t6=Q}},
        }

\tikzset{d/.style={flipflop, flipflop def={
        t1=D, t3=$\!\!>\mathrm{CK}$, t4={\ctikztextnot{Q}},
        t6=Q}}
        }

\newcommand{\parspace}{\vspace{0.1cm}}
\definecolor{battleshipgrey}{rgb}{0.52, 0.52, 0.51}
\linespread{1.25}
\geometry{tmargin=.7in, bmargin=.75in, lmargin=.75in, rmargin = .75in}

\begin{document}
\setlength{\parindent}{0mm}

\title{Portes Logiques}
\author{Aubin SIONVILLE}
\date{MPI Clemenceau - 2021-2023}
\maketitle

\part*{Logique Combinatoire}
\section*{Portes}
\begin{multicols}{3}
    
    \centering\subsection*{Porte ET}
    \begin{tikzpicture}
        \draw (0,0) node[ieeestd and port] (and1) {};
        \draw (and1.in 1) node[anchor=east] {A};
        \draw (and1.in 2) node[anchor=east] {B};
        \draw (and1.out) node[anchor=west] {S};
        \draw (3.75,0) node[european and port] (and2) {};
        \draw (and2.in 1) node[anchor=east] {A};
        \draw (and2.in 2) node[anchor=east] {B};
        \draw (and2.out) node[anchor=west] {S};
    \end{tikzpicture}
    
    \parspace

    \begin{circuitikz}
        \draw (0,0) to [battery1] (0,1.5)
        to [switch, l=$A$] (2,1.5)
        to [switch, l=$B$] (3.5,1.5)
        to [short] (4,1.5) to [lamp, l=$S$] (4,0) to [short] (0,0);
    \end{circuitikz}
    
    \centering\subsection*{Porte OU}
    \begin{tikzpicture}
        \draw (0,0) node[ieeestd or port] (or1) {};
        \draw (or1.in 1) node[anchor=east] {A};
        \draw (or1.in 2) node[anchor=east] {B};
        \draw (or1.out) node[anchor=west] {S};
        \draw (3.75,0) node[european or port] (or2) {};
        \draw (or2.in 1) node[anchor=east] {A};
        \draw (or2.in 2) node[anchor=east] {B};
        \draw (or2.out) node[anchor=west] {S};
    \end{tikzpicture}

    \parspace

    \begin{circuitikz}
        \draw (0,0) to [battery1] (0,1.5)
        to [short] (0.5, 1.5)
        to [short] (0.5, 2)
        to [switch, l=$A$] (2.5,2)
        to [short] (2.5, 1.5)
        to [short] (3.5, 1.5)
        to [lamp, l=$S$] (3.5,0) to [short] (0,0);
        \draw (0.5, 1.5) to [short] (0.5, 1)
        to [switch, l=$B$] (2.5,1)
        to [short] (2.5, 1.5);
    \end{circuitikz}

    \centering\subsection*{Porte NON}
    \begin{tikzpicture}
        \draw (0,0) node[ieeestd not port] (not1) {};
        \draw (not1.in) node[anchor=east] {A};
        \draw (not1.out) node[anchor=west] {S};
        \draw (3.75,0) node[european not port] (not2) {};
        \draw (not2.in) node[anchor=east] {A};
        \draw (not2.out) node[anchor=west] {S};
    \end{tikzpicture}

    \parspace
    \parspace
    \parspace
    \parspace
    \parspace
    \parspace
    \parspace

    \begin{circuitikz}
        \draw (0,0) to [battery1] (0,1.5)
        to [short] (3, 1.5) to [lamp, l=$S$] (3,0) to [short] (0,0);
        \draw (1.25,1.5) to [switch, l=$A$] (1.25, 0);
    \end{circuitikz}

\end{multicols}

\vspace{0.5cm}

\begin{multicols}{3}

    \centering\subsection*{Porte NON ET}
    \begin{tikzpicture}
        \draw (0,0) node[ieeestd nand port] (nand1) {};
        \draw (nand1.in 1) node[anchor=east] {A};
        \draw (nand1.in 2) node[anchor=east] {B};
        \draw (nand1.out) node[anchor=west] {S};
        \draw (3.75,0) node[european nand port] (nand2) {};
        \draw (nand2.in 1) node[anchor=east] {A};
        \draw (nand2.in 2) node[anchor=east] {B};
        \draw (nand2.out) node[anchor=west] {S};
    \end{tikzpicture}

    \parspace

    \begin{circuitikz}
        \draw (0,0) to [battery1] (0,2)
        to [short] (3, 2) to [lamp, l=$S$] (3,0) to [short] (0,0);
        \draw (1.25,2) to [switch, l=$A$] (1.25, 1)
        to [switch, l=$B$] (1.25,0);
    \end{circuitikz}


    \centering\subsection*{Porte NON OU}
    \begin{tikzpicture}
        \draw (0,0) node[ieeestd nor port] (nor1) {};
        \draw (nor1.in 1) node[anchor=east] {A};
        \draw (nor1.in 2) node[anchor=east] {B};
        \draw (nor1.out) node[anchor=west] {S};
        \draw (3.75,0) node[european nor port] (nor2) {};
        \draw (nor2.in 1) node[anchor=east] {A};
        \draw (nor2.in 2) node[anchor=east] {B};
        \draw (nor2.out) node[anchor=west] {S};
    \end{tikzpicture}

    \parspace

    \begin{circuitikz}
        \draw (0,0) to [battery1] (0,1.5)
        to [short] (4.5, 1.5) to [lamp, l=$S$] (4.5,0) to [short] (0,0);
        \draw (1.25,1.5) to [switch, l=$A$] (1.25, 0);
        \draw (3,1.5) to [switch, l=$B$] (3, 0);
    \end{circuitikz}

    \centering\subsection*{Porte OU EXCLUSIF}
    \begin{tikzpicture}
        \draw (0,0) node[ieeestd xor port] (xor1) {};
        \draw (xor1.in 1) node[anchor=east] {A};
        \draw (xor1.in 2) node[anchor=east] {B};
        \draw (xor1.out) node[anchor=west] {S};
        \draw (3.75,0) node[european xor port] (xor2) {};
        \draw (xor2.in 1) node[anchor=east] {A};
        \draw (xor2.in 2) node[anchor=east] {B};
        \draw (xor2.out) node[anchor=west] {S};
    \end{tikzpicture}

    \parspace

    \begin{circuitikz}
        \draw (0,0) to [battery1] (0,1.5)
        to [short] (0.5, 1.5)
        to [switch, l=$A$] (2.5,1.5)
        to [short] (4.5, 1.5)
        to [lamp, l=$S$] (4.5,0) to [short] (0,0);
        \draw (0.5, 1.5) to [short] (0.5, 2.25)
        to [short] (2.5, 2.25)
        to [switch, l=$B$] (3.5,2.25)
        to [short] (3.5, 1.5);
        \draw (0.5, 1.5) to [short] (0.5, 0.75)
        to [switch] (2.5, 0.75)
        to [switch] (3.5, 0.75)
        to [short] (3.5, 0);
        \draw [dashed] (1.5, 1) to [short] (1.5, 1.45);
        \draw [dashed] (3, 1) to [short] (3, 2.2);
    \end{circuitikz}
\end{multicols}

\newpage

\centering\part*{Logique Séquentielle}

\section*{Stabilité}
Système stable $\iff$ tant qu'on ne change pas les entrées, les sorties ne changent pas.
\begin{multicols}{2}
    \subsection*{Exemple stable}
    \begin{tikzpicture}
        \ctikzset{
            logic ports=ieee,
        }
        % Two NOT gates in series
        % Connect the output of the first to the input of the second
        % and connect the output of the second to the input of the first (feedback)
        \draw (0,0) node[ieeestd not port] (not1) {};
        \draw (2,0) node[ieeestd not port] (not2) {};

        \draw (not1.out) to [short, l=$u_1$] (not2.in 1);
        \draw (not2.out) to [short, l=$s$] ++(0.25, 0)
        to [short] ++(0, -0.75)
        to [short] (-1, -0.75)
        to [short] (-1, 0)
        to [short, l=$e$] (not1.in 1);
    \end{tikzpicture}

    \centering\subsection*{Exemple instable}
    
    \begin{tikzpicture}
        \ctikzset{
            logic ports=ieee,
        }
        % Three NOT gates in series
        % Connect the output of the first to the input of the second
        % connect the output of the second to the input of the third
        % and connect the output of the third to the input of the first (feedback)
        \draw (0,0) node[ieeestd not port] (not1) {};
        \draw (2,0) node[ieeestd not port] (not2) {};
        \draw (4,0) node[ieeestd not port] (not3) {};

        \draw (not1.out) to [short, l=$u_1$] (not2.in 1);
        \draw (not2.out) to [short, l=$u_2$] (not3.in 1);
        \draw (not3.out) to [short, l=$s$] ++(0.25, 0)
        to [short] ++(0, -0.75)
        to [short] (-1, -0.75)
        to [short] (-1, 0)
        to [short, l=$e$] (not1.in 1);
    \end{tikzpicture}
\end{multicols}

\centering\section*{Bascule RS}
\begin{multicols}{2}
    
    \subsection*{Table de vérité}
    \begin{tabular}{|c|c|c|c|c|}
        \hline
        $R$ & $S$ & $Q_n$ & $Q_{n+1}$ & Action \\
        \hline
        0 & 0 & $Q_n$ & $Q_n$ & Mémorisation \\
        0 & 1 & 0 & 1 & Inscription\\
        1 & 0 & 1 & 0 & Effacement\\
        \rowcolor{battleshipgrey!80}
        1 & 1 & $Q_n$ & ? & ?\\
        \hline
    \end{tabular}
    
    \subsection*{Symbole}
    \begin{tikzpicture}
        \draw (0,0) node[sr] {};

    \end{tikzpicture}

\end{multicols}
\vspace{0.5cm}

\begin{multicols}{2}
    \centering\subsection*{Bascule RS à inscription prioritaire}
    \parspace
    \begin{tikzpicture}
        % Two NAND gates one above the other
        \draw (0,0) node[ieeestd nand port] (nand1) {};
        \draw (0,3) node[ieeestd nand port] (nand2) {};

        % Connect both inputs of the first NAND gate
        \draw (nand1.in 2) to (nand1.in 1);
        % Connect both inputs of the second NAND gate
        \draw (nand2.in 2) to (nand2.in 1);
        % Make R come from the left in the first NAND gate
        \draw (-1.075,0) to [short] ++(-0.5, 0);
        % Write R in a node at the left of this line
        \draw (-1.5,0) node[left] {$R$};
        % Make S come from the left in the second NAND gate
        \draw (-1.075,3) to [short] ++(-0.5, 0);
        % Write S in a node at the left of this line
        \draw (-1.5,3) node[left] {$S$};


        % Two NAND gates one above the other on the right
        \draw (4,0.27) node[ieeestd nand port] (nand3) {};
        \draw (4,2.73) node[ieeestd nand port] (nand4) {};

        % Connect the outputs of the first two NAND gates to the inputs of the second two NAND gates
        \draw (nand1.out) to [short] (nand3.in 2);
        \draw (nand2.out) to [short] (nand4.in 1);

        % Connect the two outputs to the inputs (feedback)
        \draw (nand3.out) to [short] ++(1, 0) node[right] {$\overline{Q}$};
        \draw (nand3.out) to [short] ++(0.5, 0)
        to [short] ++(0, 0.5)
        to [short] ++(-3, 1.68)
        to [short] (nand4.in 2);
        \draw (nand4.out) to [short] ++(1, 0) node[right] {$Q$};
        \draw (nand4.out) to [short] ++(0.5, 0)
        to [short] ++(0, -0.5)
        to [short] ++(-3, -1.68)
        to [short] (nand3.in 1);
    \end{tikzpicture}

    \centering\subsection*{Bascule RS à effacement prioritaire}
    \begin{tikzpicture}

        % Two NOR gates one above the other on the right
        \draw (0,0.27) node[ieeestd nor port] (nor1) {};
        \draw (0,2.73) node[ieeestd nor port] (nor2) {};

        \draw (nor1.in 2) to ++(-0.5, 0) node[left] {$R$};
        \draw (nor2.in 1) to ++(-0.5, 0) node[left] {$S$};

        % Connect the two outputs to the inputs (feedback)
        \draw (nor1.out) to [short] ++(1, 0) node[right] {$Q$};
        \draw (nor1.out) to [short] ++(0.5, 0)
        to [short] ++(0, 0.5)
        to [short] ++(-3.25, 1.68)
        to [short] (nor2.in 2);
        \draw (nor2.out) to [short] ++(1, 0) node[right] {$\overline{Q}$};
        \draw (nor2.out) to [short] ++(0.5, 0)
        to [short] ++(0, -0.5)
        to [short] ++(-3.25, -1.68)
        to [short] (nor1.in 1);
    \end{tikzpicture}
\end{multicols}

\section*{Verrou D}
C'est une bascule RS qui est activée par un signal (typiquement un signal d'horloge) et qui conserve son état jusqu'à modification par un autre signal. On dit qu'elle est "synchrone".\\
C'est utile pour stocker des données et fabriquer des registres.

\begin{multicols}{2}
    \subsection*{Symbole}
    \begin{tikzpicture}
        \draw (0,0) node[d] {};
    \end{tikzpicture}

    \subsection*{Construction}
    \begin{tikzpicture}
        % A NOT gate
        \draw (0,0) node[ieeestd not port] (not1) {};
        \draw (2, 0.28) node[ieeestd and port] (and1) {};
        \draw (2, 1.961) node[ieeestd and port] (and2) {};
        \draw (4.5, 1.121) node[sr] {};

        \draw (not1.out) to [short] (and1.in 2);
        \draw (and1.out) to [short] ++(0.5,0);
        \draw (and2.out) to [short] ++(0.5,0);

        \draw (not1.in 1) to [short] ++(-1,0) node[left] {$D$};
        \draw (not1.in 1) to [short] ++(-0.5,0)
        to [short] ++(0,2.22)
        to [short] (and2.in 1);
        
        \draw (and1.in 1) to [short] (and2.in 2);
        \draw (and1.in 1) to [short] ++(0, 0.5)
        to [short] ++(-1, 0) node[left] {$\mathrm{CK}$};

    \end{tikzpicture}

\end{multicols}

\end{document}